`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/01 18:07:17
// Design Name: 
// Module Name: band_switch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module band_switch
#(
    parameter FMC_DATA_WIDTH = 16,
    parameter FMC_CMD_WIDTH = 8
)
(
        input                                  ui_clk,
        input                                  rst,    //resetn 
	    input [FMC_DATA_WIDTH-1:0]             h_active,  //H_P
        input [FMC_DATA_WIDTH-1:0]             v_active,  //V_P
        output reg[19:0]                       fifo_max_addr,
        output reg[4:0]                        wr_bank_addr,
        output reg[4:0]                        rd_bank_addr,
        input [FMC_CMD_WIDTH-1:0]              bmp_num,
        input                                  frame_write_done
    );
    
	always @(posedge ui_clk or posedge rst)begin
        if(rst)
           fifo_max_addr<= 20'd0;
        else
           fifo_max_addr<= h_active*v_active/10;//h_active*v_active*24/240;
    end
    
    reg frame_write_done_d0;
    always @(posedge ui_clk or posedge rst)begin
        if(rst)
           frame_write_done_d0<=1'b0;
        else 
           frame_write_done_d0<= frame_write_done; 
    end
    
    reg [4:0] bmp_num_tep;
    always @(posedge ui_clk or posedge rst)begin
        if(rst) begin
           wr_bank_addr<= 5'd0;
           rd_bank_addr<= 5'd0;
           bmp_num_tep <= 5'd0;
        end
        else if(~frame_write_done_d0 & frame_write_done) begin //rasing
           wr_bank_addr<= bmp_num; //wr_bank_addr+1'b1;
           rd_bank_addr<= wr_bank_addr;
           bmp_num_tep<=bmp_num;
        end
        else if(frame_write_done_d0 & frame_write_done & bmp_num_tep != bmp_num) begin
           wr_bank_addr<= bmp_num; //wr_bank_addr+1'b1;
           rd_bank_addr<= wr_bank_addr;
           bmp_num_tep<=bmp_num;
        end
        else begin
           wr_bank_addr<= wr_bank_addr;
           rd_bank_addr<= rd_bank_addr;
           bmp_num_tep <= bmp_num_tep;
        end
    end
    
    
endmodule
